Fix STM32F1 motor shocks (stepper timer issue) (#14030)
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@ -42,14 +42,10 @@
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// Local defines
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// --------------------------------------------------------------------------
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#define NUM_HARDWARE_TIMERS 4
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//#define PRESCALER 1
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// --------------------------------------------------------------------------
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// Types
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// --------------------------------------------------------------------------
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// --------------------------------------------------------------------------
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// Public Variables
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// --------------------------------------------------------------------------
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@ -57,19 +53,7 @@
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// --------------------------------------------------------------------------
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// Private Variables
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// --------------------------------------------------------------------------
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/* VGPV
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const tTimerConfig TimerConfig [NUM_HARDWARE_TIMERS] = {
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{ TC0, 0, TC0_IRQn, 0}, // 0 - [servo timer5]
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{ TC0, 1, TC1_IRQn, 0}, // 1
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{ TC0, 2, TC2_IRQn, 0}, // 2
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{ TC1, 0, TC3_IRQn, 2}, // 3 - stepper
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{ TC1, 1, TC4_IRQn, 15}, // 4 - temperature
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{ TC1, 2, TC5_IRQn, 0}, // 5 - [servo timer3]
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{ TC2, 0, TC6_IRQn, 0}, // 6
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{ TC2, 1, TC7_IRQn, 0}, // 7
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{ TC2, 2, TC8_IRQn, 0}, // 8
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};
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*/
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// --------------------------------------------------------------------------
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// Function prototypes
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// --------------------------------------------------------------------------
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@ -101,11 +85,14 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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case 3: irq_num = NVIC_TIMER3; break;
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case 4: irq_num = NVIC_TIMER4; break;
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case 5: irq_num = NVIC_TIMER5; break;
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#ifdef STM32_HIGH_DENSITY
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// 6 & 7 are basic timers, avoid them
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case 8: irq_num = NVIC_TIMER8_CC; break;
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#endif
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default:
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/**
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* We should not get here, add Sanitycheck for timer number. Should be a general timer
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* since basic timers do not have CC channels.
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* Advanced timers should be skipped if possible too, and are not listed above.
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* This should never happen. Add a Sanitycheck for timer number.
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* Should be a general timer since basic timers have no CC channels.
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*/
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break;
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}
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@ -118,23 +105,27 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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switch (timer_num) {
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case STEP_TIMER_NUM:
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timer_pause(STEP_TIMER_DEV);
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timer_set_mode(STEP_TIMER_DEV, STEP_TIMER_CHAN, TIMER_OUTPUT_COMPARE); // counter
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timer_set_count(STEP_TIMER_DEV, 0);
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timer_set_prescaler(STEP_TIMER_DEV, (uint16_t)(STEPPER_TIMER_PRESCALE - 1));
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timer_set_reload(STEP_TIMER_DEV, 0xFFFF);
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timer_oc_set_mode(STEP_TIMER_DEV, STEP_TIMER_CHAN, TIMER_OC_MODE_FROZEN, TIMER_OC_NO_PRELOAD); // no output pin change
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timer_set_compare(STEP_TIMER_DEV, STEP_TIMER_CHAN, MIN(hal_timer_t(HAL_TIMER_TYPE_MAX), (STEPPER_TIMER_RATE / frequency)));
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timer_no_ARR_preload_ARPE(STEP_TIMER_DEV); // Need to be sure no preload on ARR register
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timer_attach_interrupt(STEP_TIMER_DEV, STEP_TIMER_CHAN, stepTC_Handler);
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nvic_irq_set_priority(irq_num, 1);
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nvic_irq_set_priority(irq_num, STEP_TIMER_IRQ_PRIO);
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timer_generate_update(STEP_TIMER_DEV);
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timer_resume(STEP_TIMER_DEV);
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break;
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case TEMP_TIMER_NUM:
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timer_pause(TEMP_TIMER_DEV);
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timer_set_mode(TEMP_TIMER_DEV, TEMP_TIMER_CHAN, TIMER_OUTPUT_COMPARE);
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timer_set_count(TEMP_TIMER_DEV, 0);
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timer_set_prescaler(TEMP_TIMER_DEV, (uint16_t)(TEMP_TIMER_PRESCALE - 1));
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timer_set_reload(TEMP_TIMER_DEV, 0xFFFF);
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timer_set_compare(TEMP_TIMER_DEV, TEMP_TIMER_CHAN, MIN(hal_timer_t(HAL_TIMER_TYPE_MAX), ((F_CPU / TEMP_TIMER_PRESCALE) / frequency)));
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timer_attach_interrupt(TEMP_TIMER_DEV, TEMP_TIMER_CHAN, tempTC_Handler);
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nvic_irq_set_priority(irq_num, 2);
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nvic_irq_set_priority(irq_num, TEMP_TIMER_IRQ_PRIO);
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timer_generate_update(TEMP_TIMER_DEV);
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timer_resume(TEMP_TIMER_DEV);
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break;
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@ -145,7 +136,6 @@ void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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switch (timer_num) {
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case STEP_TIMER_NUM: ENABLE_STEPPER_DRIVER_INTERRUPT(); break;
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case TEMP_TIMER_NUM: ENABLE_TEMPERATURE_INTERRUPT(); break;
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default: break;
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}
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}
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@ -153,12 +143,11 @@ void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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switch (timer_num) {
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case STEP_TIMER_NUM: DISABLE_STEPPER_DRIVER_INTERRUPT(); break;
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case TEMP_TIMER_NUM: DISABLE_TEMPERATURE_INTERRUPT(); break;
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default: break;
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}
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}
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static inline bool timer_irq_enabled(const timer_dev * const dev, const uint8_t interrupt) {
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return bool(*bb_perip(&(dev->regs).adv->DIER, interrupt));
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return bool(*bb_perip(&(dev->regs).gen->DIER, interrupt));
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}
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bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
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@ -208,7 +197,7 @@ timer_dev* get_timer_dev(int number) {
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case 12: return &timer12;
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#endif
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#if STM32_HAVE_TIMER(13)
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case 13: return &timer14;
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case 13: return &timer13;
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#endif
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#if STM32_HAVE_TIMER(14)
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case 14: return &timer14;
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@ -45,7 +45,7 @@
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typedef uint16_t hal_timer_t;
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#define HAL_TIMER_TYPE_MAX 0xFFFF
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#define HAL_TIMER_RATE (F_CPU) // frequency of timers peripherals
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#define HAL_TIMER_RATE uint32_t(F_CPU) // frequency of timers peripherals
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#define STEP_TIMER_CHAN 1 // Channel of the timer to use for compare and interrupts
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#define TEMP_TIMER_CHAN 1 // Channel of the timer to use for compare and interrupts
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@ -60,6 +60,9 @@ typedef uint16_t hal_timer_t;
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#define PULSE_TIMER_NUM STEP_TIMER_NUM
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#define SERVO0_TIMER_NUM 1 // SERVO0 or BLTOUCH
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#define STEP_TIMER_IRQ_PRIO 1
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#define TEMP_TIMER_IRQ_PRIO 2
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#define TEMP_TIMER_PRESCALE 1000 // prescaler for setting Temp timer, 72Khz
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#define TEMP_TIMER_FREQUENCY 1000 // temperature interrupt frequency
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@ -126,43 +129,38 @@ bool HAL_timer_interrupt_enabled(const uint8_t timer_num);
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*/
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FORCE_INLINE static void HAL_timer_set_compare(const uint8_t timer_num, const hal_timer_t compare) {
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//compare = MIN(compare, HAL_TIMER_TYPE_MAX);
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switch (timer_num) {
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case STEP_TIMER_NUM:
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timer_set_compare(STEP_TIMER_DEV, STEP_TIMER_CHAN, compare);
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return;
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// NOTE: WE have set ARPE = 0, which means the Auto reload register is not preloaded
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// and there is no need to use any compare, as in the timer mode used, setting ARR to the compare value
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// will result in exactly the same effect, ie trigerring an interrupt, and on top, set counter to 0
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timer_set_reload(STEP_TIMER_DEV, compare); // We reload direct ARR as needed during counting up
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break;
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case TEMP_TIMER_NUM:
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timer_set_compare(TEMP_TIMER_DEV, TEMP_TIMER_CHAN, compare);
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return;
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default:
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return;
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}
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}
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FORCE_INLINE static hal_timer_t HAL_timer_get_compare(const uint8_t timer_num) {
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switch (timer_num) {
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case STEP_TIMER_NUM:
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return timer_get_compare(STEP_TIMER_DEV, STEP_TIMER_CHAN);
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case TEMP_TIMER_NUM:
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return timer_get_compare(TEMP_TIMER_DEV, TEMP_TIMER_CHAN);
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default:
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return 0;
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break;
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}
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}
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FORCE_INLINE static void HAL_timer_isr_prologue(const uint8_t timer_num) {
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switch (timer_num) {
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case STEP_TIMER_NUM:
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timer_set_count(STEP_TIMER_DEV, 0);
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// No counter to clear
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timer_generate_update(STEP_TIMER_DEV);
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return;
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case TEMP_TIMER_NUM:
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timer_set_count(TEMP_TIMER_DEV, 0);
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timer_generate_update(TEMP_TIMER_DEV);
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return;
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default:
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return;
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}
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}
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#define HAL_timer_isr_epilogue(TIMER_NUM)
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// No command is available in framework to turn off ARPE bit, which is turned on by default in libmaple.
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// Needed here to reset ARPE=0 for stepper timer
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FORCE_INLINE static void timer_no_ARR_preload_ARPE(timer_dev *dev) {
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bb_peri_set_bit(&(dev->regs).gen->CR1, TIMER_CR1_ARPE_BIT, 0);
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}
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#define TIMER_OC_NO_PRELOAD 0 // Need to disable preload also on compare registers.
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@ -1262,7 +1262,7 @@ void Stepper::isr() {
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// Program timer compare for the maximum period, so it does NOT
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// flag an interrupt while this ISR is running - So changes from small
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// periods to big periods are respected and the timer does not reset to 0
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HAL_timer_set_compare(STEP_TIMER_NUM, HAL_TIMER_TYPE_MAX);
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HAL_timer_set_compare(STEP_TIMER_NUM, hal_timer_t(HAL_TIMER_TYPE_MAX));
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// Count of ticks for the next ISR
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hal_timer_t next_isr_ticks = 0;
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