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Backtrace formatting cleanup

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This commit is contained in:
Scott Lahteine 2018-04-04 20:23:41 -05:00
parent 902c885782
commit 4b25543633
2 changed files with 79 additions and 80 deletions
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2
Marlin/src/backtrace/unwarm.cpp
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@ -118,7 +118,7 @@ bool UnwReportRetAddr(UnwState * const state, uint32_t addr) {
} }
// Go backwards to the previous word // Go backwards to the previous word
pf -= 4;; pf -= 4;
} }
} }

61
Marlin/src/backtrace/unwarm_arm.cpp
View File

@ -33,18 +33,18 @@
*/ */
static bool isDataProc(uint32_t instr) { static bool isDataProc(uint32_t instr) {
uint8_t opcode = (instr & 0x01e00000) >> 21; uint8_t opcode = (instr & 0x01E00000) >> 21;
bool S = (instr & 0x00100000) ? true : false; bool S = (instr & 0x00100000) ? true : false;
if((instr & 0xfc000000) != 0xe0000000) { if ((instr & 0xFC000000) != 0xE0000000) {
return false; return false;
} else }
if(!S && opcode >= 8 && opcode <= 11) { else if (!S && opcode >= 8 && opcode <= 11) {
/* TST, TEQ, CMP and CMN all require S to be set */ /* TST, TEQ, CMP and CMN all require S to be set */
return false; return false;
} else {
return true;
} }
else
return true;
} }
UnwResult UnwStartArm(UnwState * const state) { UnwResult UnwStartArm(UnwState * const state) {
@ -78,8 +78,8 @@ UnwResult UnwStartArm(UnwState * const state) {
* This is tested prior to data processing to prevent * This is tested prior to data processing to prevent
* mis-interpretation as an invalid TEQ instruction. * mis-interpretation as an invalid TEQ instruction.
*/ */
if((instr & 0xfffffff0) == 0xe12fff10) { if ((instr & 0xFFFFFFF0) == 0xE12FFF10) {
uint8_t rn = instr & 0xf; uint8_t rn = instr & 0xF;
UnwPrintd4("BX r%d\t ; r%d %s\n", rn, rn, M_Origin2Str(state->regData[rn].o)); UnwPrintd4("BX r%d\t ; r%d %s\n", rn, rn, M_Origin2Str(state->regData[rn].o));
@ -98,10 +98,9 @@ UnwResult UnwStartArm(UnwState * const state) {
UnwPrintd2(" Return PC=%x\n", state->regData[15].v & (~0x1)); UnwPrintd2(" Return PC=%x\n", state->regData[15].v & (~0x1));
/* Report the return address */ /* Report the return address */
if(!UnwReportRetAddr(state, state->regData[rn].v)) { if (!UnwReportRetAddr(state, state->regData[rn].v))
return UNWIND_TRUNCATED; return UNWIND_TRUNCATED;
} }
}
/* Determine the return mode */ /* Determine the return mode */
if (state->regData[rn].v & 0x1) { if (state->regData[rn].v & 0x1) {
@ -118,16 +117,16 @@ UnwResult UnwStartArm(UnwState * const state) {
} }
} }
/* Branch */ /* Branch */
else if((instr & 0xff000000) == 0xea000000) { else if ((instr & 0xFF000000) == 0xEA000000) {
int32_t offset = (instr & 0x00ffffff); int32_t offset = (instr & 0x00FFFFFF);
/* Shift value */ /* Shift value */
offset = offset << 2; offset = offset << 2;
/* Sign extend if needed */ /* Sign extend if needed */
if (offset & 0x02000000) { if (offset & 0x02000000) {
offset |= 0xfc000000; offset |= 0xFC000000;
} }
UnwPrintd2("B %d\n", offset); UnwPrintd2("B %d\n", offset);
@ -142,11 +141,11 @@ UnwResult UnwStartArm(UnwState * const state) {
} }
/* MRS */ /* MRS */
else if((instr & 0xffbf0fff) == 0xe10f0000) { else if ((instr & 0xFFBF0FFF) == 0xE10F0000) {
#if defined(UNW_DEBUG) #if defined(UNW_DEBUG)
bool R = (instr & 0x00400000) ? true : false; bool R = (instr & 0x00400000) ? true : false;
#endif #endif
uint8_t rd = (instr & 0x0000f000) >> 12; uint8_t rd = (instr & 0x0000F000) >> 12;
UnwPrintd4("MRS r%d,%s\t; r%d invalidated", rd, R ? "SPSR" : "CPSR", rd); UnwPrintd4("MRS r%d,%s\t; r%d invalidated", rd, R ? "SPSR" : "CPSR", rd);
@ -154,7 +153,7 @@ UnwResult UnwStartArm(UnwState * const state) {
state->regData[rd].o = REG_VAL_INVALID; state->regData[rd].o = REG_VAL_INVALID;
} }
/* MSR */ /* MSR */
else if((instr & 0xffb0f000) == 0xe120f000) { else if ((instr & 0xFFB0F000) == 0xE120F000) {
#if defined(UNW_DEBUG) #if defined(UNW_DEBUG)
bool R = (instr & 0x00400000) ? true : false; bool R = (instr & 0x00400000) ? true : false;
@ -172,13 +171,13 @@ UnwResult UnwStartArm(UnwState * const state) {
/* Data processing */ /* Data processing */
else if (isDataProc(instr)) { else if (isDataProc(instr)) {
bool I = (instr & 0x02000000) ? true : false; bool I = (instr & 0x02000000) ? true : false;
uint8_t opcode = (instr & 0x01e00000) >> 21; uint8_t opcode = (instr & 0x01E00000) >> 21;
#if defined(UNW_DEBUG) #if defined(UNW_DEBUG)
bool S = (instr & 0x00100000) ? true : false; bool S = (instr & 0x00100000) ? true : false;
#endif #endif
uint8_t rn = (instr & 0x000f0000) >> 16; uint8_t rn = (instr & 0x000F0000) >> 16;
uint8_t rd = (instr & 0x0000f000) >> 12; uint8_t rd = (instr & 0x0000F000) >> 12;
uint16_t operand2 = (instr & 0x00000fff); uint16_t operand2 = (instr & 0x00000FFF);
uint32_t op2val; uint32_t op2val;
int op2origin; int op2origin;
@ -203,8 +202,8 @@ UnwResult UnwStartArm(UnwState * const state) {
/* Decode operand 2 */ /* Decode operand 2 */
if (I) { if (I) {
uint8_t shiftDist = (operand2 & 0x0f00) >> 8; uint8_t shiftDist = (operand2 & 0x0F00) >> 8;
uint8_t shiftConst = (operand2 & 0x00ff); uint8_t shiftConst = (operand2 & 0x00FF);
/* rotate const right by 2 * shiftDist */ /* rotate const right by 2 * shiftDist */
shiftDist *= 2; shiftDist *= 2;
@ -217,7 +216,7 @@ UnwResult UnwStartArm(UnwState * const state) {
else { else {
/* Register and shift */ /* Register and shift */
uint8_t rm = (operand2 & 0x000f); uint8_t rm = (operand2 & 0x000F);
uint8_t regShift = (operand2 & 0x0010) ? true : false; uint8_t regShift = (operand2 & 0x0010) ? true : false;
uint8_t shiftType = (operand2 & 0x0060) >> 5; uint8_t shiftType = (operand2 & 0x0060) >> 5;
uint32_t shiftDist; uint32_t shiftDist;
@ -229,7 +228,7 @@ UnwResult UnwStartArm(UnwState * const state) {
/* Get the shift distance */ /* Get the shift distance */
if (regShift) { if (regShift) {
uint8_t rs = (operand2 & 0x0f00) >> 8; uint8_t rs = (operand2 & 0x0F00) >> 8;
if (operand2 & 0x00800) { if (operand2 & 0x00800) {
@ -249,7 +248,7 @@ UnwResult UnwStartArm(UnwState * const state) {
UnwPrintd7("%s r%d\t; r%d %s r%d %s", shiftMnu[shiftType], rs, rm, M_Origin2Str(state->regData[rm].o), rs, M_Origin2Str(state->regData[rs].o)); UnwPrintd7("%s r%d\t; r%d %s r%d %s", shiftMnu[shiftType], rs, rm, M_Origin2Str(state->regData[rm].o), rs, M_Origin2Str(state->regData[rs].o));
} }
else { else {
shiftDist = (operand2 & 0x0f80) >> 7; shiftDist = (operand2 & 0x0F80) >> 7;
op2origin = REG_VAL_FROM_CONST; op2origin = REG_VAL_FROM_CONST;
if (shiftDist) { if (shiftDist) {
@ -281,11 +280,11 @@ UnwResult UnwStartArm(UnwState * const state) {
/* Register shifts maybe greater than 32 */ /* Register shifts maybe greater than 32 */
if (shiftDist >= 32) { if (shiftDist >= 32) {
op2val = 0xffffffff; op2val = 0xFFFFFFFF;
} }
else { else {
op2val = state->regData[rm].v >> shiftDist; op2val = state->regData[rm].v >> shiftDist;
op2val |= 0xffffffff << (32 - shiftDist); op2val |= 0xFFFFFFFF << (32 - shiftDist);
} }
} }
else { else {
@ -305,7 +304,7 @@ UnwResult UnwStartArm(UnwState * const state) {
} }
else { else {
/* Limit shift distance to 0-31 incase of register shift */ /* Limit shift distance to 0-31 incase of register shift */
shiftDist &= 0x1f; shiftDist &= 0x1F;
op2val = (state->regData[rm].v >> shiftDist) | op2val = (state->regData[rm].v >> shiftDist) |
(state->regData[rm].v << (32 - shiftDist)); (state->regData[rm].v << (32 - shiftDist));
@ -441,15 +440,15 @@ UnwResult UnwStartArm(UnwState * const state) {
/* Block Data Transfer /* Block Data Transfer
* LDM, STM * LDM, STM
*/ */
else if((instr & 0xfe000000) == 0xe8000000) { else if ((instr & 0xFE000000) == 0xE8000000) {
bool P = (instr & 0x01000000) ? true : false; bool P = (instr & 0x01000000) ? true : false;
bool U = (instr & 0x00800000) ? true : false; bool U = (instr & 0x00800000) ? true : false;
bool S = (instr & 0x00400000) ? true : false; bool S = (instr & 0x00400000) ? true : false;
bool W = (instr & 0x00200000) ? true : false; bool W = (instr & 0x00200000) ? true : false;
bool L = (instr & 0x00100000) ? true : false; bool L = (instr & 0x00100000) ? true : false;
uint16_t baseReg = (instr & 0x000f0000) >> 16; uint16_t baseReg = (instr & 0x000F0000) >> 16;
uint16_t regList = (instr & 0x0000ffff); uint16_t regList = (instr & 0x0000FFFF);
uint32_t addr = state->regData[baseReg].v; uint32_t addr = state->regData[baseReg].v;
bool addrValid = M_IsOriginValid(state->regData[baseReg].o); bool addrValid = M_IsOriginValid(state->regData[baseReg].o);
int8_t r; int8_t r;